BER Analyzer

SV Technologies BER Analyzer Unit (Model No SSP/BER/04) consists of two parts a Transmitter and a Receiver, both of which work independently. The Transmission section consists of a Data Generator, which generates a pseudo­ random bit sequence patterns at the selected clock rate. The Receiver consists of an Error Detector co-located with the Data Generator, which receives the data and clock from the external device under test and measures the bit error rate of the received data.

The unit generates data and clock at various standard code lengths of 27 -1, 215-1, 2 20-1 and 223-1, and at the selected clock rates in the range of 0-200Mbps.The code lengths and the Clock rates can be selected through the keypad interface or from remote control computer. The Data Generator and Error Detector can be controlled from remote control through GPIB/RS-232 or user specified remote control interface. The data generator generates the data at a rate selected by the selected clock source in the unit.

Data Generator and Error Detector Circuit together are implemented in an FPGA, which is programmed for the required function. The device is driven by a DDS synthesizer, which acts as one of the clock sources, for the clock rate selection with a resolution of 1KHz. The required clock can also be selected internally within the FPGA from a PLL implemented in the FPGA.

Salient features

  • Clock generation up to 200 Mbps  from  DDS (Direct Digital Synthesizers) through front    panel keypad
  • Selection with a resolution of 1 KHz.
  • PRBS data generation at different code lengths selectable among 27 -1, 215-1, 2 20-1 and    223-1.
  • Error Detector is co-located with Data Generator and independently operable. Entire BER    Analyzer circuit is incorporated in a single device (FPGA).
  • User interface and selection either from front panel through keypad or from remote control    through
  • GPIB/RS-232 etc.